/*
 * linux-4.9/drivers/media/platform/sunxi-vin/vin-video/dma140_reg_i.h
 *
 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
 *
 * Authors:  Zhao Wei <zhaowei@allwinnertech.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#ifndef __CSIC__DMA140__REG__I__H__
#define __CSIC__DMA140__REG__I__H__

/*
 * Detail information of registers
 */
#define	CSIC_DMA_TOP_EN_REG_OFF			0X000
#define	CSIC_DMA_TOP_EN				0
#define CSIC_DMA_TOP_EN_MASK			(0X1 << CSIC_DMA_TOP_EN)
#define	CSIC_CLK_CNT_EN				1
#define	CSIC_CLK_CNT_EN_MASK			(0X1 << CSIC_CLK_CNT_EN)
#define	CSIC_CLK_CNT_SPL			2
#define	CSIC_CLK_CNT_SPL_MASK			(0X1 << CSIC_CLK_CNT_SPL)
#define	CSIC_FRAME_CNT_EN			5
#define	CSIC_FRAME_CNT_EN_MASK			(0X1 << CSIC_FRAME_CNT_EN)
#define	CSIC_VI_TO_CNT_EN			6
#define	CSIC_VI_TO_CNT_EN_MASK			(0X1 << CSIC_VI_TO_CNT_EN)
#define	CSIC_MIN_SDR_WR_SIZE			8
#define	CSIC_MIN_SDR_WR_SIZE_MASK		(0X3 << CSIC_MIN_SDR_WR_SIZE)
#define	CSIC_VE_ONLINE_HS_EN			12
#define	CSIC_VE_ONLINE_HS_EN_MASK		(0X1 << CSIC_VE_ONLINE_HS_EN)
#define	CSIC_VE_ONLINE_CH_SEL			13
#define	CSIC_VE_ONLINE_CH_SEL_MASK		(0X3 << CSIC_VE_ONLINE_CH_SEL)
#define	CSIC_FLIP_SIZE_CFG_MODE 		28
#define	CSIC_FLIP_SIZE_CFG_MODE_MASK    	(0X1 << CSIC_FLIP_SIZE_CFG_MODE)
#define	CSIC_BUF_LENGTH_CFG_MODE		29
#define	CSIC_BUF_LENGTH_CFG_MODE_MASK   	(0X1 << CSIC_BUF_LENGTH_CFG_MODE)
#define	CSIC_VFLIP_BUF_ADDR_CFG_MODE    	30
#define	CSIC_VFLIP_BUF_ADDR_CFG_MODE_MASK	(0X1 << CSIC_VFLIP_BUF_ADDR_CFG_MODE)
#define	CSIC_VER_EN    				31
#define	CSIC_VER_EN_MASK			(0X1 << CSIC_VER_EN)

#define	CSIC_DMA_MUL_CH_CFG_REG_OFF		0X004
#define	MUL_CH_EN				0
#define	MUL_CH_EN_MASK				(0X1 << MUL_CH_EN)
#define	CUR_IN_CH				16
#define	CUR_IN_CH_MASK				(0X3 << CUR_IN_CH)
#define	CUR_OUT_CH				20
#define	CUR_OUT_CH_MASK				(0X3 << CUR_OUT_CH)


#define	CSIC_DMA_VE_FRM_CNT_REG_OFF		0X050
#define	FRM_ST_CNT				0
#define	FRM_ST_CNT_MASK				(0XFF << FRM_ST_CNT)
#define	FRM_DONE_CNT				16
#define	FRM_DONE_CNT_MASK			(0XFF << FRM_DONE_CNT)

#define	CSIC_DMA_VE_LINE_CNT_REG_OFF		0X054
#define	LINE_ST_CNT				0
#define	LINE_ST_CNT_MASK			(0X3FF << LINE_ST_CNT)
#define	LINE_DONE_CNT				16
#define	LINE_DONE_CNT_MASK			(0X3FF << LINE_DONE_CNT)

#define	CSIC_DMA_VE_CUR_FRM_ADDR_REG_OF		0X058
#define	CUR_FRM_ADDR				0
#define	CUR_FRM_ADDR_MASK			(0XFFFFFFFF << CUR_FRM_ADDR)


#define	CSIC_DMA_VE_LAST_FRM_ADDR_REG_OFF	0X05C
#define	LAST_FRM_ADDR				0
#define	LAST_FRM_ADDR_MASK			(0XFFFFFFFF << LAST_FRM_ADDR)

#define	CSIC_DMA_TOP_INT_EN_REG_OFF		0X100

#define	CSIC_DMA_TOP_INT_STA_REG_OFF		0X104
#define	FS_PUL_INT_PD				0
#define	FS_PUL_INT_PD_MASK			(0X1 << FS_PUL_INT_PD)
#define	CLR_FS_FRM_CNT_INT_PD			1
#define	CLR_FS_FRM_CNT_INT_PD_MASK		(0X1 << CLR_FS_FRM_CNT_INT_PD)
#define	VI_INP_TO_INT_PD			2
#define	VI_INP_TO_INT_PD_MASK			(0X1 << VI_INP_TO_INT_PD)
#define TOP_INT_ALL_MASK			0x7


#define	CSIC_DMA_VER_REG_OFF			0X1F0
#define	VER_BIG_VER				0
#define	VER_BIG_VER_MASK			(0X3 << VER_BIG_VER)
#define	VER_SMALL_VER				0
#define	VER_SMALL_VER_MASK			(0X3 << VER_SMALL_VER)

#define	CSIC_DMA_CH_OFF				0X200
#define	CSIC_DMA_EN_REG_OFF			0X200
#define	CAP_EN					0
#define	CAP_EN_MASK				(0X1 << CAP_EN)
#define	LBC_EN					1
#define	LBC_EN_MASK				(0X1 << LBC_EN)
#define	FRM_DROP_EN				8
#define	FRM_DROP_EN_MASK			(0X1 << FRM_DROP_EN)

#define	CSIC_DMA_CFG_REG_OFF			0X204
#define	CAP_MASK_NUM				2
#define	CAP_MASK_NUM_MASK			(0XF << CAP_MASK_NUM)
#define	FPS_DS					6
#define	FPS_DS_MASK				(0XF << FPS_DS)
#define	FIELD_SEL				10
#define	FIELD_SEL_MASK				(0X3 << FIELD_SEL)
#define	HFLIP_EN				12
#define	HFLIP_EN_MASK				(0X1 << HFLIP_EN)
#define	VFLIP_EN				13
#define	VFLIP_EN_MASK				(0X1 << VFLIP_EN)
#define	OUTPUT_FMT				16
#define	OUTPUT_FMT_MASK				(0XF << OUTPUT_FMT)
#define	ENABLE_10BIT_CUT2_8BIT			21
#define	ENABLE_10BIT_CUT2_8BIT_MASK		(0X1 << ENABLE_10BIT_CUT2_8BIT)

#define	CSIC_LOST_FRM_CNT_REG_OFF		0X208
#define	FRM_LOST_CNT				0
#define	FRM_LOST_CNT_MASK			(0XFF << FRM_LOST_CNT)
#define	FRM_LOST_CNT_EN				31
#define	FRM_LOST_CNT_EN_MASK			(0X1 << FRM_LOST_CNT_EN)

#define	CSIC_DMA_HSIZE_REG_OFF			0X210
#define	HOR_START				0
#define	HOR_START_MASK				(0X3FFF << HOR_START)
#define	HOR_LEN					16
#define	HOR_LEN_MASK				(0X3FFF << HOR_LEN)

#define	CSIC_DMA_VSIZE_REG_OFF			0X214
#define	VER_START				0
#define	VER_START_MASK				(0X3FFF << VER_START)
#define	VER_LEN					16
#define	VER_LEN_MASK				(0X3FFF << VER_LEN)

#define	CSIC_DMA_F0_BUFA_REG_OFF		0X220
#define	F0_BUFA					0
#define	F0_BUFA_MASK				(0XFFFFFFFF << F0_BUFA)

#define	CSIC_DMA_F1_BUFA_REG_OFF		0X228
#define	F1_BUFA					0
#define	F1_BUFA_MASK				(0XFFFFFFFF << F1_BUFA)

#define	CSIC_DMA_F2_BUFA_REG_OFF		0X230
#define	F2_BUFA					0
#define	F2_BUFA_MASK				(0XFFFFFFFF << F2_BUFA)

#define	CSIC_DMA_BUF_LEN_REG_OFF		0X238
#define	BUF_LEN					0
#define	BUF_LEN_MASK				(0X3FFF << BUF_LEN)
#define	BUF_LEN_C				16
#define	BUF_LEN_C_MASK				(0X3FFF << BUF_LEN_C)

#define	CSIC_DMA_FLIP_SIZE_REG_OFF		0X23C
#define	VALID_LEN				0
#define	VALID_LEN_MASK				(0X3FFF << VALID_LEN)
#define	VER_LEN					16
#define	VER_LEN_MASK				(0X3FFF << VER_LEN)

#define	CSIC_DMA_CAP_STA_REG_OFF		0X24C
#define	SCAP_STA				0
#define	SCAP_STA_MASK				(0X1 << SCAP_STA)
#define	FIELD_STA				2
#define	FIELD_STA_MASK				(0X1 << FIELD_STA)

#define	CSIC_DMA_INT_EN_REG_OFF			0X250
#define	CD_INT_EN				0
#define	CD_INT_EN_MASK				(0X1 << CD_INT_EN)
#define	FD_INT_EN				1
#define	FD_INT_EN_MASK				(0X1 << FD_INT_EN)
#define	FIFO0_OF_INT_EN				2
#define	FIFO0_OF_INT_EN_MASK			(0X1 << FIFO0_OF_INT_EN)
#define	LC_INT_EN				5
#define	LC_INT_EN_MASK				(0X1 << LC_INT_EN)
#define	HB_OF_INT_EN				6
#define	HB_OF_INT_EN_MASK			(0X1 << HB_OF_INT_EN)
#define	VS_INT_EN				7
#define	VS_INT_EN_MASK				(0X1 << VS_INT_EN)
#define	BUF_ADDR_FIFO_INT_EN			13
#define	BUF_ADDR_FIFO_INT_EN_MASK  		(0X1 << BUF_ADDR_FIFO_INT_EN)
#define	STORED_FRM_CNT_INT_EN   		14
#define	STORED_FRM_CNT_INT_EN_MASK		(0X1 << STORED_FRM_CNT_INT_EN)
#define	FRM_LOST_INT_EN 			15
#define	FRM_LOST_INT_EN_MASK			(0X1 << FRM_LOST_INT_EN)
#define	LBC_HB_INT_EN				16
#define	LBC_HB_INT_EN_MASK			(0X1 << LBC_HB_INT_EN)
#define	BUF_ADDR_UNDERFLOW_INT_EN 		17
#define	BUF_ADDR_UNDERFLOW_INT_EN_MASK		(0X1 << BUF_ADDR_UNDERFLOW_INT_EN)
#define	BUF_ADDR_OVERFLOW_INT_EN 		18
#define	BUF_ADDR_OVERFLOW_INT_EN_MASK		(0X1 << BUF_ADDR_OVERFLOW_INT_EN)


#define	CSIC_DMA_INT_STA_REG_OFF		0X254
#define	CD_PD					0
#define	CD_PD_MASK				(0X1 << CD_PD)
#define	FD_PD					1
#define	FD_PD_MASK				(0X1 << FD_PD)
#define	FIFO0_OF_PD				2
#define	FIFO0_OF_PD_MASK			(0X1 << FIFO0_OF_PD)
#define	FIFO1_OF_PD				3
#define	FIFO1_OF_PD_MASK			(0X1 << FIFO1_OF_PD)
#define	FIFO2_OF_PD				4
#define	FIFO2_OF_PD_MASK			(0X1 << FIFO2_OF_PD)
#define	LC_PD					5
#define	LC_PD_MASK				(0X1 << LC_PD)
#define	HB_OF_PD				6
#define	HB_OF_PD_MASK				(0X1 << HB_OF_PD)
#define	VS_PD					7
#define	VS_PD_MASK				(0X1 << VS_PD)
#define	BUF_ADDR_FIFO_INT_PD			13
#define	BUF_ADDR_FIFO_INT_PD_MASK  		(0X1 << BUF_ADDR_FIFO_INT_PD)
#define	STORED_FRM_CNT_INT_PD   		14
#define	STORED_FRM_CNT_INT_PD_MASK		(0X1 << STORED_FRM_CNT_INT_PD)
#define	FRM_LOST_INT_PD 			15
#define	FRM_LOST_INT_PD_MASK			(0X1 << FRM_LOST_INT_PD)
#define	LBC_HB_INT_PD				16
#define	LBC_HB_INT_PD_MASK			(0X1 << LBC_HB_INT_PD)
#define	BUF_ADDR_UNDERFLOW_INT_PD 		17
#define	BUF_ADDR_UNDERFLOW_INT_PD_MASK		(0X1 << BUF_ADDR_UNDERFLOW_INT_PD)
#define	BUF_ADDR_OVERFLOW_INT_PD 		18
#define	BUF_ADDR_OVERFLOW_INT_PD_MASK		(0X1 << BUF_ADDR_OVERFLOW_INT_PD)

#define	CSIC_DMA_LINE_CNT_REG_OFF		0X258
#define	LINE_CNT_NUM				0
#define	LINE_CNT_NUM_MASK			(0X1FFF << LINE_CNT_NUM)

#define CSIC_DMA_FRM_CNT_REG_OFF		0X05C
#define CSIC_DMA_CLR_DIS			16
#define CSIC_DMA_CLR_DIS_MASK			(0X7FFF << CSIC_DMA_CLR_DIS)
#define CSIC_DMA_FRM_CNT			0
#define CSIC_DMA_FRM_CNT_MASK			(0XFFFF << CSIC_DMA_FRM_CNT)

#define	CSIC_LBC_CONFIGURE_REG_OFF		0X300
#define	LIMIT_QP_MIM				0
#define	LIMIT_QP_MIM_MASK  			(0X7 << LIMIT_QP_MIM)
#define	LIMIT_QP_ENABLE 			3
#define	LIMIT_QP_ENABLE_MASK 			(0X1 << LIMIT_QP_ENABLE)
#define	UPDATE_ADVANTURE_RATIO  		16
#define	UPDATE_ADVANTURE_RATIO_MASK     	(0X1F << UPDATE_ADVANTURE_RATIO)
#define	UPDATE_ADVANTURE_ENABLE 		21
#define	UPDATE_ADVANTURE_ENABLE_MASK    	(0X1 << UPDATE_ADVANTURE_ENABLE)
#define	MSQ_ENABLE				24
#define	MSQ_ENABLE_MASK  			(0X1 << MSQ_ENABLE)
#define	OTS_ENABLE				25
#define	OTS_ENABLE_MASK  			(0X1 << OTS_ENABLE)
#define	DTS_ENABLE				26
#define	DTS_ENABLE_MASK  			(0X1 << DTS_ENABLE)
#define	GLB_ENABLE				27
#define	GLB_ENABLE_MASK  			(0X1 << GLB_ENABLE)
#define	WHETHER_LOSSY_ENABLE			31
#define	WHETHER_LOSSY_ENABLE_MASK 		(0X1 << WHETHER_LOSSY_ENABLE)

#define	CSIC_LBC_LINE_TARGET_BIT0_REG_OFF	0X304
#define	CMP_TRG_BIT_FOR_EVEN_LINE		0
#define	CMP_TRG_BIT_FOR_EVEN_LINE_MASK   	(0XFFFFF << CMP_TRG_BIT_FOR_EVEN_LINE)

#define	CSIC_LBC_LINE_TARGET_BIT1_REG_OFF	0X308
#define	CMP_TRG_BIT_FOR_ODD_LINE		0
#define	CMP_TRG_BIT_FOR_ODD_LINE_MASK   	(0XFFFFF << CMP_TRG_BIT_FOR_ODD_LINE)

#define	CSIC_LBC_RC_ADV_REG_OFF  		0X30C
#define	RATE_CONTROL_ADVANTURE_0		0
#define	RATE_CONTROL_ADVANTURE_0_MASK   	(0XFF << RATE_CONTROL_ADVANTURE_0)
#define	RATE_CONTROL_ADVANTURE_1		8
#define	RATE_CONTROL_ADVANTURE_1_MASK   	(0XFF << RATE_CONTROL_ADVANTURE_1)
#define	RATE_CONTROL_ADVANTURE_2		16
#define	RATE_CONTROL_ADVANTURE_2_MASK   	(0XFF << RATE_CONTROL_ADVANTURE_2)
#define	RATE_CONTROL_ADVANTURE_3		24
#define	RATE_CONTROL_ADVANTURE_3_MASK   	(0XFF << RATE_CONTROL_ADVANTURE_3)

#define	CSIC_LBC_MB_MIN_REG_OFF  		0X310
#define	MACROBLOCK_MIN_BITS0			0
#define	MACROBLOCK_MIN_BITS0_MASK  		(0XFF << MACROBLOCK_MIN_BITS0)
#define	MACROBLOCK_MIN_BITS1			16
#define	MACROBLOCK_MIN_BITS1_MASK  		(0XFF << MACROBLOCK_MIN_BITS1)

#endif /*__CSIC__DMA140__REG__I__H__*/
